Flash memory devices have been known for many years. Standard flash memory devices known in the art store data in a memory array, arranged in groups, called pages and/or blocks.
An example of a NAND flash memory device known in the art is Micron Technologies device No. MT29F2G08AABWP. The Data Sheet (herein under—DS) of this device is incorporated by reference for all purposes as if fully set forth herein.
When a Host (e.g. computer, controller or other similar device which a flash memory is connected to), which the flash memory device is connected to, exchanges data with the flash memory device, an entire data page is usually written to the memory array or read out of the memory array simultaneously, within one operation, from/to an internal buffer (or register) called a page buffer.
When the Host asserts a request instructing the flash memory device to read a page of data, the page of data is transferred from the memory array to the page buffer. The Host is allowed to assert a request instructing the flash memory device to start a new operation only after the page of data is fully read into the page buffer.
The time spent for data exchange between the Host and the flash memory device includes both Host  Buffer and Buffer  Memory Array transfer periods. As the data page size of existing flash memory devices increases, the Host  Buffer transfer time increases as well, and becomes comparable to the Buffer  Memory Array transfer time.
For example, in a NAND flash memory device known in the art having a 2 KByte data page, the Host  Buffer transfer time is typically 50 to 100 microseconds per page, while Buffer  Memory Array page read time is 20 to 50 microseconds per page and Buffer  Memory Array page program (write) time is 200 to 800 microseconds per page.
Therefore, in order to increase the system's throughput, some flash memory devices include an additional data buffer—a cache buffer—for enabling a simultaneous data transfer between the Host and this cache buffer and between the page buffer and the memory array.
When a cache buffer is implemented in the flash memory device, the page of data is read from the memory array to the page buffer and then promptly transferred to the cache buffer, thus “freeing” the page buffer for receiving the next page of data from the memory array. In other words, the Host is allowed to assert a request to the flash memory device to read a next page of data from the memory array even before the previous page of data is fully transferred out of the cache buffer.
Therefore, implementing a cache buffer for page read operation substantially decreases the transfer delay time and increases the system's throughput.
A read operation using a cache buffer is called “Cache Read” or “Read with Cache” or “Cache Mode Page Read” (all depending on a specific flash device vendor). The read operation is responsive to specific commands triggered from the Host.
In reality, flash memory devices are provided for reading large amounts of data that are sequentially written to the flash memory. An example is a cluster of a file system containing several Kbytes of data, which is always written to and read from the flash memory device by the operating system as one “chunk”. Other examples include information, which are “streamed” by a multimedia source (e.g. video, audio recording system), or an image taken by a digital camera.
In these cases it is likely that the next page of data, required to be read from the flash memory device, is a physically consecutive page of data stored in a memory array. Flash memory devices known in the art use this assumption when implementing a cache buffer for page read operation. For example, if the current read operation reads a page data from address N of the memory array, then the following cache read operation always retrieves a page data from address N+1 of the memory array.
However, there is a possibility that the “next consecutive page” assumption is no longer valid. One of such cases is an application, in which there is a need to read data pages in a “reverse” order, implementing, as an example, a LIFO (last-in-first-out) procedure. Implementing such an application may be required in a system that records events of different types over time and requires the option to look back for the recently recorded events of a certain type from time to time. In such systems, using the address of the last record (i.e. page of data) in order to quickly read a “previous” page of data may be very beneficial.
Existing flash memory devices used for cache reading operations are not configured to answer such needs. In other words, flash memory devices known in the art that include a cache buffer are not able to provide reading of pages of data in the “reverse” order (i.e. with decreasing page to page address). In order to achieve reading a “previous” page of data, existing methods simply apply a “regular” (not cached) page read operation and do not employ the cache buffer.
However, applying a “regular” page read operation degrades the system's throughput, in comparison with a regular cache read operation.